Tutorial 11 - Sequential Logic Systems

Learning Objectives

• recall the circuit diagram of a bistable latch based on NAND gates and describe its operation and function;

• recall the symbol for a rising edge triggered D-type flip-flop and describe its operation and function;

• recall that in a shift register information is passed along from one element to the next on each clock pulse;

• recall how rising edge triggered D-type flip-flops can be used to form a shift register and describe its operation and applications.

What is a sequential circuit?

We have looked at combinational logic systems in which the output was determined by the combinations of one or more inputs.  The output state at any time is dependent on the state of the inputs.  In a sequential circuit, the output is dependent on:

• The current input to the circuit;

• The previous inputs to the circuit.

In effect the circuit has a memory.

Sequential circuits are the basic building blocks of:

• Counters;

• Shift registers;

• Memories.

In synchronous sequential circuits, changes in output do not occur immediately there is a change in input, but the next time there is a clock pulse.  In asynchronous circuits the next stage is triggered by the completion of the previous stage without reference to a clock pulse.

Clock pulses are square wave oscillations that are produced by a pulse generator that can be based on two kinds of circuit:

• Astable generators produce trains of square waves;

• Monostables produce single pulses.

Circuits are triggered in one of two ways:

• Level triggering in which the changes occur when the level of the pulse is either at 0 or 1.

• Edge triggering in which the change occurs as the clock pulse rises from 0 to 1(rising or positive edge) or from 1 to 0 (falling or negative edge).

The diagram shows the idea. Level sensitive devices are often referred to as latches, while edge triggered devices are called flip-flops.  Pulses can be provided manually with switches, but they can provide spurious pulses due to bounce.  They can be de-bounced using a Schmitt trigger, which also can be used to clean up noisy signals.

 What is the difference between pulses produced by a monostable and an astable? What is the behaviour you would expect from a synchronous falling edge triggered flip-flop?

Here some important definitions to learn.

 Term Definition Combinational circuit The output is determined by the combinations of one or more inputs. Sequential circuit Output is dependent on: The current input to the circuit; The previous inputs to the circuit. Synchronous Changes in output do not occur immediately there is a change in input, but the next time there is a clock pulse Asynchronous The next stage is triggered by the completion of the previous stage without reference to a clock pulse Triggering Level triggering in which the changes occur when the level of the pulse is either at 0 or 1. Edge triggering in which the change occurs as the clock pulse rises from 0 to 1(rising or positive edge) or from 1 to 0 (falling or negative edge). Flip-Flop Edge triggered devices are called flip-flops. Latch Level sensitive devices are often referred to as latches

Bistable Latches

Bistables have two stable states; one output remains high while the other remains low.  These are complementary states.  The situation remains until an external input signal such as a clock pulse switches the complimentary states over.

We can use two NAND gates to produce an S-bar - R-bar latch.  The circuit diagram is shown below. There are two inputs to the latch, the set, S-bar, and the reset, R-bar.  There are two output states, Q and Q-bar which are complementary to each other.  This means that when Q = 0, Q-bar = 1, and vice versa.  The common symbol for the latch is not the circuit diagram above, but either of the alternatives shown. This bistable is the industry standard, made from NAND gates.  We say that its inputs are active-low which means that the state changes when the inputs go low.

We can draw up a truth table, often called a transition table for the circuit.  We can also show what is happening in a timing diagram, which is three voltage-time graphs stacked one on top of the other.

 S-bar R-bar Q Q-bar Notes 0 1 1 0 S-bar = 0 sets Q = 1 (SET) 1 1 1 0 Outputs remain in previous states 1 0 0 1 R-bar = 0 sets Q-bar = 1 and Q = 0 (RESET) 1 1 0 1 Outputs remain in previous states 0 0 0 0 Indeterminate state (not allowed) When S-bar falls from 1 to 0, there is no effect until the R-bar falls from 1 to 0.  Then the output Q changes from 1 to 0.  Then R-bar goes to 1, but there is no change in Q until S-bar goes to 1.

This  latch is a circuit that can be used to de-bounce a switch, cleaning its action to get rid of unwanted pulses.  The layout is shown in the diagram: Let us analyse the circuit as the switch is moved from B to A.

 Switch Position S-bar R-bar Q 1 0 0 1 1 0 0 1 1 1 1 1 0 1 1

Notice how the output does not change as the switch bounces.

There is one disadvantage about the S – R bistable circuit, and that is what happens when both the inputs are 0.  This is an indeterminate state and the output is not predictable.  We cannot say if the bistable will return to the SET or the RESET state.  We can avoid this by ensuring that the inputs are changed alternately.

 What is the problem with there being an indeterminate state?

The D-type Flop-Flip

Latches can be used to act as memories, but have a major problem.  They can be what is called transparent.  If one of the inputs is high, and the other is connected to a clock impulse, the output will change as the clock pulses pass through.  Let us think about this more using the S – R latch (made from NOR gates).  Data is put in through the S input while the R input is connected to a square wave pulse generator as below. This latch is active high, which means that it changes state when S or R goes high.  We start off with R low and S changing from low to high and back again.  The output Q is low.  Then we change R to high and this should give us a high at the output Q.  We get that initially, but when the input S goes low, the output goes low.  When it goes high, the output goes high as well.  This situation lasts as long as R stays high.  So we get the clock pulse passing through the latch, which is why we call it transparent.  This can be a nuisance in computers and other systems where data changes rapidly.

We can overcome this problem by using edge-triggering.  Bistables that use edge triggering are called flip-flops.  Flip-flops do not have this problem with being transparent.  The D-type flip-flop is the basic design unit for sequential circuits, which are circuits whose outputs change with time.  The symbol with the D-type flop-flip is shown. We should note the following about the flip-flop:

• The outputs are complimentary.  When Q is 1, Q-bar is 0 and vice versa.

• Terminal S and R are there to set and reset the flip-flop.  Signals at these inputs take priority over the other two inputs

• The data input takes in the data, while the clock input takes in the clock pulses.  The triangle indicates edge triggering.  An upward pointing arrow indicates positive edge triggering, while a downward arrow shows negative edge triggering.

• CMOS flip-flops are active high, while many TTL flip-flops are active low.

The behaviour of the flip-flop is shown. When we send a pulse down the SET or RESET lines, the results can be shown in the truth table:

 S R Q Q-bar 0 0 1/0 0/1 0 1 0 1 1 0 1 0 1 1 1 1 What is meant by a circuit being transparent?

Using D-type Flip-flops to Make a Shift Register

Shift registers are important components in computers.  They act as memories for binary numbers, and are important in shifting data about the computer.  Data may be received in serial form, i.e. one digit after another, but is sent in whole words through the computer.  Each bit of a word needs its own wire to travel in, therefore for a 4-byte word (1 byte = 8 bits, therefore 32 bits) needs 32 parallel connectors.  This is called parallel data transmission.

Very high speeds are possible because of the parallel connectors, buses, that form the highways between computer components.  The diagram shows the difference between serial and parallel data transmission. Why is the printer cable that comes from a parallel port on a computer is so thick and heavy?

D type flip-flops are used to enable this in these ways:

• Serial input serial output (SISO)

• Parallel input parallel output (PIPO)

• Serial input parallel output (SIPO)

•  Parallel input serial output (PISO)

We will look at a four-bit serial input parallel output shift register. • The resets are all connected so that the circuit can be cleared to 0 at the same time.

• At the rising edge of the clock input, the output takes on the value of the data input.

• The set inputs are not connected.

• The Q-bar outputs are not used.

• The Q subscripts refer to the power of 2.  Q2 carries the 22 (4) bit.

We are going to put the number 1101 into the register to see how this works and the table below shows the sequence of events.

 Clock pulse Q3 Q2 Q1 Q0 Notes 0 0 0 0 0 1 1 0 0 0 2 0 1 0 0 3 1 0 1 0 4 1 1 0 1 Data loaded 5 0 1 1 0 6 0 0 1 1 7 0 0 0 1 8 0 0 0 0 Data out

The timing diagram is shown here: We can use the timing diagram to explain what is happening:

• On the clock pulse F1 changes Q3 from 0 to 1.

• This sets F2 to change Q2 at the second rising edge from 0 to 1.

• Which in turn changes F3 and so on.

• F1 changes back from 1 to 0 on the second rising edge.

• followed by F2 and F3 in turn.

• The Table shows the data being loaded by the 4th clock pulse.

 Can you use the timing diagram to explain how a SIPO shift register works?

Monostable Circuits based on NAND gates

Here is a monostable circuit based on a NAND gate: What is meant by the term monostable?

How does the circuit work?  At first the circuit is stable.

• When switch S is open, the point L is at 1.

• The capacitor C is not charged and the voltage at M is 0.

• Therefore the output of Y is 1, and both inputs of X are 1.

• The output of X is 0.

•  Since the inputs of Z are 1, and the output of Z is 0.

Now let us momentarily close the switch S.

• T becomes 0.

• Therefore the input L into gate X becomes 0.

• The output of X becomes 1.

• The flow of charge onto the capacitor C causes there to be a current through the resistor R.  This makes the voltage at M high.

• Therefore gate Y gives out a 0.

• Since the voltage at N is a zero, the output of gate Z is 1, and the LED lights up.

 What does gate Z do and why?

This lasts a short time, determined by the RC time constant.

• The current through R decays exponentially as the capacitor charges up.  So the voltage at M decays exponentially as well.

• As the voltage at M drops, it passes below the threshold at which Y is triggered to change state.

• Gate Y gives out a 0 until the voltage passes below the threshold.

• Now gate Y changes to 1.

• Since L is at 1, this makes the output of X low again.

If the switch is held closed, the output of X remains 1, but no current flows onto the plates of the capacitor, so the voltage at M remains low.  Therefore holding the switch has no effect on the behaviour of the circuit. We can show the behaviour of the circuit with timing diagrams for each of the points. Depending on the threshold at which the gate triggers, it can be shown that the time period T at for which the output of Z is high is approximately RC.

If the gate triggers at 0.5 Vs, then T  is approximately 0.7 RC.

 Why does the voltage at M show the shape shown?

NAND gate Astable

We can make an astable circuit the output of which oscillates at a frequency determined by the value of the time constant of a capacitor and a resistor. If you look carefully at the arrangements of the NAND gates, it does not take a genius to see that the two NAND gates are wired as NOT gates, so this set up is also called a NOT gate astable.  Let’s have a look at how the circuit works:

• Suppose the output of Y is high.

• This means that the input to Y is low.

• The capacitor will charge up.

•  A current flows through the resistor R which means there will be a voltage across it.

• This raises the input to Y to high and it will trigger to the output being low.

• Since X is connected to the feedback loop, its output will be low.

• The low output of X will cause the capacitor to discharge.

• This makes the input to Y low, hence the output to go to high.

• And so on…

We can summarise this in the timing diagram: We can show that the mark time is given by the relationship:

tH =1.1 RC

Similarly the space time is given by:

tL »1.1 RC

Therefore the period:

T = tH + tL = 2.2 RC

So the frequency:

f = 1/T = 1/2.2 RC

 A NAND gate monostable has a capacitor of capacitance 20 mF with a resistor of resistance 150 kW.  What is the period of the monostable?

 Links Web tutorial Animation for sequential systems Shift Registers (intro)