Tutorial 11 - Sequential Logic Systems

 Learning Objectives

 

 

 

What is a sequential circuit?

We have looked at combinational logic systems in which the output was determined by the combinations of one or more inputs.  The output state at any time is dependent on the state of the inputs.  In a sequential circuit, the output is dependent on:

In effect the circuit has a memory.

 

Sequential circuits are the basic building blocks of:

In synchronous sequential circuits, changes in output do not occur immediately there is a change in input, but the next time there is a clock pulse.  In asynchronous circuits the next stage is triggered by the completion of the previous stage without reference to a clock pulse.

 

Clock pulses are square wave oscillations that are produced by a pulse generator that can be based on two kinds of circuit:

 

Circuits are triggered in one of two ways:

 

The diagram shows the idea.

 

Level sensitive devices are often referred to as latches, while edge triggered devices are called flip-flops.  Pulses can be provided manually with switches, but they can provide spurious pulses due to bounce.  They can be de-bounced using a Schmitt trigger, which also can be used to clean up noisy signals.

 

 ANSWER

 

Question 1

What is the difference between pulses produced by a monostable and an astable? 

Answer

Question 2

What is the behaviour you would expect from a synchronous falling edge triggered flip-flop? 

Answer

 

Here some important definitions to learn.

 

 

Term

Definition

Combinational circuit

The output is determined by the combinations of one or more inputs.

Sequential circuit

 

 Output is dependent on:

  • The current input to the circuit;

  • The previous inputs to the circuit.

Synchronous

Changes in output do not occur immediately there is a change in input, but the next time there is a clock pulse

Asynchronous

The next stage is triggered by the completion of the previous stage without reference to a clock pulse

Triggering

 

 

Level triggering in which the changes occur when the level of the pulse is either at 0 or 1.

Edge triggering in which the change occurs as the clock pulse rises from 0 to 1(rising or positive edge) or from 1 to 0 (falling or negative edge).

Flip-Flop

Edge triggered devices are called flip-flops.

 

Latch

Level sensitive devices are often referred to as latches

 

Bistable Latches

Bistables have two stable states; one output remains high while the other remains low.  These are complementary states.  The situation remains until an external input signal such as a clock pulse switches the complimentary states over.

 

We can use two NAND gates to produce an S-bar - R-bar latch.  The circuit diagram is shown below.

 

 

There are two inputs to the latch, the set, S-bar, and the reset, R-bar.  There are two output states, Q and Q-bar which are complementary to each other.  This means that when Q = 0, Q-bar = 1, and vice versa.  The common symbol for the latch is not the circuit diagram above, but either of the alternatives shown.

 

 

This bistable is the industry standard, made from NAND gates.  We say that its inputs are active-low which means that the state changes when the inputs go low.

 

We can draw up a truth table, often called a transition table for the circuit.  We can also show what is happening in a timing diagram, which is three voltage-time graphs stacked one on top of the other.

 

S-bar

R-bar

Q

Q-bar

Notes

0

1

1

0

S-bar = 0 sets Q = 1 (SET)

1

1

1

0

Outputs remain in previous states

1

0

0

1

R-bar = 0 sets Q-bar = 1 and Q = 0 (RESET)

1

1

0

1

Outputs remain in previous states

0

0

0

0

Indeterminate state (not allowed)

 

 

When S-bar falls from 1 to 0, there is no effect until the R-bar falls from 1 to 0.  Then the output Q changes from 1 to 0.  Then R-bar goes to 1, but there is no change in Q until S-bar goes to 1.

This  latch is a circuit that can be used to de-bounce a switch, cleaning its action to get rid of unwanted pulses.  The layout is shown in the diagram:

 

 

Let us analyse the circuit as the switch is moved from B to A.

 

Switch Position

 

S-bar

 

R-bar

 

Q

 

 

1

 

0

 

0

 

 

 

1

 

1

 

0

 

 

 

0

 

1

 

1

 

 

 

1

 

1

 

1

 

 

 

 

0

 

1

 

1

 

Notice how the output does not change as the switch bounces.

 

There is one disadvantage about the S – R bistable circuit, and that is what happens when both the inputs are 0.  This is an indeterminate state and the output is not predictable.  We cannot say if the bistable will return to the SET or the RESET state.  We can avoid this by ensuring that the inputs are changed alternately.

 

Question 3

What is the problem with there being an indeterminate state?

Answer

 

 

The D-type Flop-Flip

Latches can be used to act as memories, but have a major problem.  They can be what is called transparent.  If one of the inputs is high, and the other is connected to a clock impulse, the output will change as the clock pulses pass through.  Let us think about this more using the S – R latch (made from NOR gates).  Data is put in through the S input while the R input is connected to a square wave pulse generator as below.

 

 

 

This latch is active high, which means that it changes state when S or R goes high.  We start off with R low and S changing from low to high and back again.  The output Q is low.  Then we change R to high and this should give us a high at the output Q.  We get that initially, but when the input S goes low, the output goes low.  When it goes high, the output goes high as well.  This situation lasts as long as R stays high.  So we get the clock pulse passing through the latch, which is why we call it transparent.  This can be a nuisance in computers and other systems where data changes rapidly.

 

We can overcome this problem by using edge-triggering.  Bistables that use edge triggering are called flip-flops.  Flip-flops do not have this problem with being transparent.  The D-type flip-flop is the basic design unit for sequential circuits, which are circuits whose outputs change with time.  The symbol with the D-type flop-flip is shown.

 

 

We should note the following about the flip-flop:

  The behaviour of the flip-flop is shown.

 

When we send a pulse down the SET or RESET lines, the results can be shown in the truth table:

 

S

R

Q

Q-bar

0

0

1/0

0/1

0

1

0

1

1

0

1

0

1

1

1

1

 

 


 

Question 4

What is meant by a circuit being transparent?

Answer

 

Using D-type Flip-flops to Make a Shift Register

Shift registers are important components in computers.  They act as memories for binary numbers, and are important in shifting data about the computer.  Data may be received in serial form, i.e. one digit after another, but is sent in whole words through the computer.  Each bit of a word needs its own wire to travel in, therefore for a 4-byte word (1 byte = 8 bits, therefore 32 bits) needs 32 parallel connectors.  This is called parallel data transmission.

Very high speeds are possible because of the parallel connectors, buses, that form the highways between computer components.  The diagram shows the difference between serial and parallel data transmission.

Question 5

Why is the printer cable that comes from a parallel port on a computer is so thick and heavy?

Answer

 

D type flip-flops are used to enable this in these ways:

We will look at a four-bit serial input parallel output shift register.

We are going to put the number 1101 into the register to see how this works and the table below shows the sequence of events.

 

Clock pulse

Q3

Q2

Q1

Q0

Notes

0

0

0

0

0

 

1

1

0

0

0

 

2

0

1

0

0

 

3

1

0

1

0

 

4

1

1

0

1

Data loaded

5

0

1

1

0

 

6

0

0

1

1

 

7

0

0

0

1

 

8

0

0

0

0

Data out

 The timing diagram is shown here:

We can use the timing diagram to explain what is happening:

Question 6

Can you use the timing diagram to explain how a SIPO shift register works?

Answer

 

 

Monostable Circuits based on NAND gates

Here is a monostable circuit based on a NAND gate:

 

 

 

Question 7

What is meant by the term monostable?

Answer

 

How does the circuit work?  At first the circuit is stable.

Now let us momentarily close the switch S.

Question 8

What does gate Z do and why?

Answer

 

This lasts a short time, determined by the RC time constant.

 If the switch is held closed, the output of X remains 1, but no current flows onto the plates of the capacitor, so the voltage at M remains low.  Therefore holding the switch has no effect on the behaviour of the circuit. We can show the behaviour of the circuit with timing diagrams for each of the points.

 

 

Depending on the threshold at which the gate triggers, it can be shown that the time period T at for which the output of Z is high is approximately RC.  

If the gate triggers at 0.5 Vs, then T  is approximately 0.7 RC.

 

Question 9

 Why does the voltage at M show the shape shown?

Answer

 

 

NAND gate Astable

We can make an astable circuit the output of which oscillates at a frequency determined by the value of the time constant of a capacitor and a resistor. 

 

 

If you look carefully at the arrangements of the NAND gates, it does not take a genius to see that the two NAND gates are wired as NOT gates, so this set up is also called a NOT gate astable.  Let’s have a look at how the circuit works:

  We can summarise this in the timing diagram:

 

We can show that the mark time is given by the relationship:

 tH =1.1 RC

 

Similarly the space time is given by:

 tL »1.1 RC

 

Therefore the period:

 T = tH + tL = 2.2 RC

 

So the frequency:

f = 1/T = 1/2.2 RC

 

 

 

Question 10

A NAND gate monostable has a capacitor of capacitance 20 mF with a resistor of resistance 150 kW.  What is the period of the monostable?

Answer

 

 

Links

Web tutorial

Link

Animation for sequential systems

Link

Shift Registers (intro)

Link

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